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Receiver Control Register [POR=9080h]
Bit
15
1
Bit
14
0
Bit
13
0
Bit
12
1
Bit
11
0
Bit
10
INT/VDI
Bit
9
VDIR1
Bit
8
VDIR0
Bit
7
BB2
Bit
6
BB1
Bit
5
BB0
Bit
4
GAIN1
Bit
3
GAIN0
Bit
2
RSSI2
Bit
1
RSSI1
Bit
0
RSSI0
The Receiver Control Register configures the following:
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Receiver LNA gain
Digital RSSI threshold
Receive baseband bandwidth
Valid Data Detector response time
Function of pin 16
Bit [15..11] – Command Code : These bits are the command code that is sent serially to the processor
that identifies the bits to be written to the Receiver Control Register .
Bit [10] – Pin 16 Func : Selects the function of Pin 16. See Table 10 below.
Table 10.
Pin 16 Function INT/VDI
Interrupt Input 0
Valid Data Output 1
Bit [9..8] – Valid Data Detector Response Time : When Pin 16 is selected as Valid Data Detector output
these bits set the response time in which the TRC101 will detect the incoming synchronous bit pattern
and issue an interrupt to the host processor. See Table 11 below for response settings.
Table 11.
VDI Response Time VDIR1
Fast 0
Mid 0
Slow 1
Continuous 1
VDIR0
0
1
0
1
Figure 7. VDI Signal Response Configuration
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Page 22 of 42
?by RF Monolithics, Inc.
TRC101 - 4/8/08
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